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TheSystemDevelopmentKit / rtl

Package for rtl (i.e. Verilog and VHDL ) simulation control
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Inverter testbench reads input and writes output at the same time #36

Closed Anttitarkka closed 2 years ago

Anttitarkka commented 2 years ago

Inverter testbench reads signal A and writes signal Z at posedge. Now it depends on the compiler what happens first and with Icarus Verilog the behavior is not deterministic therefore the IO files do not represent an inverter. Testbench should have some system that makes sure that input is read first.

Roenski commented 2 years ago

@Anttitarkka since I think you don't have anything else to do, you could test whether it is caused by what we assume. So, try and come up with a way to test if it helps that the inputs are always read before outputs are written (or the other way around) and see if it solves the problem. I think the first method to test is to have both $fwrite and $fscan commands in the same block. Easiest to write the testbench manually first, and if it works, then figure out what to do with the testbench generator.

Roenski commented 2 years ago

For now, this was solved by changing the inverter example so that writing happens on falling clock edge. No changes to rtl needed.