Modify rtl testbench for A-Core post route simulation

[chiplet]

Changes:

• Add vlogsimfiles property which reads a list of external module files from thesdk global variable 'VLOGLIBFILE'.
• Split rtl_timescale property into rtl_timeunit and rtl_timeprecision
• Use testbench timescale directive instead of passing a cli argument to modelsim. This is required when simulation models define their own timescales which should not be overridden by the cli argument.