Cosimulation of Verilog top + VHDL external files

[Roenski]

• Adds a routine to copy additional VHDL sources for sv models
• Adds the command for compiling additional VHDL sources for sv models
• Adds a new property, vhdlcompargs, i.e. VHDL compilation arguments
  • e.g. self.vhdlcompargs = ["-2008"]
• Bugfix: make RTL simulation run locally for interactive runs

Tested with inverter and a certain another project that runs Verilog top with additional VHDL source files.

[mkosunen]

Tested with inverter. Runs OK. I will still test this with register template after merging.