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TheSystemDevelopmentKit / rtl

Package for rtl (i.e. Verilog and VHDL ) simulation control
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Commit a1b31d7081272b breaks simulations with symlinks. #49

Closed mkosunen closed 1 year ago

mkosunen commented 1 year ago

It seems that if the symlink is relative shutil.copyfile with followsymlinks=False breaks register template simulations that have a relative symlink. like sv/register_template.sv -> ../chisel/verilog/register_template.v

@chiplet any proposals how to solve this? Should we restrict to absolute symlinks. Then those can not be version controlled.

Best way I think would be to figure out a target and create a new symlink to that.

mkosunen commented 1 year ago

I think I found a way

  1. Thest if the file is symlink https://stackoverflow.com/questions/11068419/how-to-check-if-file-is-a-symlink-in-python.
  2. find out the target and symlink to that. https://www.tutorialspoint.com/python/os_readlink.htm
mkosunen commented 1 year ago

Closed by 369c502ba48b457604b