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TheSystemDevelopmentKit / rtl

Package for rtl (i.e. Verilog and VHDL ) simulation control
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Use full paths in copying symlinks #50

Closed mkosunen closed 1 year ago

mkosunen commented 1 year ago

@chiplet @Roenski : Closes #49 . Please review.

Roenski commented 1 year ago

Shouldn't this be done for vhdl sources as well?

mkosunen commented 1 year ago

I will do the same for VHDL.

mkosunen commented 1 year ago

@Roenski this has been tested, but could you run it once?

Roenski commented 1 year ago

Yeah seems to work