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TheSystemDevelopmentKit / rtl

Package for rtl (i.e. Verilog and VHDL ) simulation control
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vhdl_testbench - signal definitions #53

Closed mkosunen closed 1 year ago

mkosunen commented 1 year ago

Define the signals from connectors

mkosunen commented 1 year ago

Closed by https://github.com/TheSystemDevelopmentKit/rtl/pull/51/commits/f59d58c1fb85de0d9c0e8c93d756c5c8493a0596