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TheSystemDevelopmentKit / rtl

Package for rtl (i.e. Verilog and VHDL ) simulation control
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vhdl-testbench - DUT instantiation #54

Closed mkosunen closed 1 year ago

mkosunen commented 1 year ago

Closed by https://github.com/TheSystemDevelopmentKit/rtl/pull/51/commits/a058e05d6dc77435084ae0090f720fdb7c3a5b81