vhdl_testbench - default clock definition - Githubissues

TheSystemDevelopmentKit / rtl

Package for rtl (i.e. Verilog and VHDL ) simulation control

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vhdl_testbench - default clock definition #55

Closed mkosunen closed 1 year ago

mkosunen commented 1 year ago

Closed by https://github.com/TheSystemDevelopmentKit/rtl/pull/51/commits/398bd66d88a2be55d3318edcfd15f1a03037a761