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TheSystemDevelopmentKit / rtl

Package for rtl (i.e. Verilog and VHDL ) simulation control
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Unify parameter definitions #63

Closed mkosunen closed 1 year ago

mkosunen commented 1 year ago

Rtl parameter definitions inside the module/entity and on command line should be of form

{ name : (type,val)}

mkosunen commented 1 year ago

Closed by https://github.com/TheSystemDevelopmentKit/rtl/pull/51/commits/5e7f4c3ec89fb7af6931968fec4cb5291313e878