Unify testbench and source code compilations with questasim

TheSystemDevelopmentKit / rtl

Package for rtl (i.e. Verilog and VHDL ) simulation control

Other

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Closed mkosunen closed 1 year ago

mkosunen commented 1 year ago

There are two simulation routines defined for questasim. Those can be merged choose the correct compilation setups based on 'model' and 'lang'

mkosunen commented 1 year ago

Closed by e61f26bd6d9b41b007c