search

TheSystemDevelopmentKit / rtl

Package for rtl (i.e. Verilog and VHDL ) simulation control
Other
1 stars 2 forks source link

Time arithmetic for event-type inputs in VHDL testbench #67

Closed mkosunen closed 1 year ago

mkosunen commented 1 year ago

Check this, might be incorrect.

mkosunen commented 1 year ago

Closed by 79ae7a6e7b45d4aa5b