Parametrized time-base for VHDL testbench - Githubissues

TheSystemDevelopmentKit / rtl

Package for rtl (i.e. Verilog and VHDL ) simulation control

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Parametrized time-base for VHDL testbench #68

Closed mkosunen closed 1 year ago

mkosunen commented 1 year ago

Closed by 79ae7a6e7b45d4aa5b

Time scaling is used only for even t based file io.