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TheSystemDevelopmentKit / rtl

Package for rtl (i.e. Verilog and VHDL ) simulation control
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WIP: `verilog_connector` fix #7

Closed chiplet closed 3 years ago

chiplet commented 3 years ago

This PR fixes an issue where verilog_connector initializes the right range limit to the parameter for the left range limit in its constructor.

chiplet commented 3 years ago

Accidentally tring to merge to master instead of v1.6_RC... Let's try again