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TheSystemDevelopmentKit / rtl

Package for rtl (i.e. Verilog and VHDL ) simulation control
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Iosync #80

Closed tjomiv closed 1 year ago

tjomiv commented 1 year ago

Currently syncing IOs with different input and output clock frequencies isn't possible (that I'm aware of), this is easily fixable by splitting rtl_io_sync to rtl_input_sync and rtl_output_sync respectively.

mkosunen commented 1 year ago

If I got it correctly I think this edit is not needed. Every iofile has the property rtl_iosync, defaulted to @(posedge clock), and you can set that separately for every iofile regardless whether it is input or output.

check inverter entity for reference.

tjomiv commented 1 year ago

You're right, I don't know why I didn't originally try that. This branch can be deleted.