Add timescale handling to questasim command

TheSystemDevelopmentKit / rtl

Package for rtl (i.e. Verilog and VHDL ) simulation control

Other

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Closed mkosunen closed 10 months ago

mkosunen commented 10 months ago

If timescale is defined in testbench, do not define it on command line.

mkosunen commented 10 months ago

@jhelande this should fix your problem.