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TheSystemDevelopmentKit / rtl

Package for rtl (i.e. Verilog and VHDL ) simulation control
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Fix control file handling #85

Closed mkosunen closed 7 months ago

mkosunen commented 10 months ago

Handle the case where no controlfile nor control contents given

mkosunen commented 10 months ago

@spelmaa2 You had problems simulationg withoutd dofiles. this should fix it. Try to remove the control contents definitions, and this should run OK.