search

TheSystemDevelopmentKit / rtl

Package for rtl (i.e. Verilog and VHDL ) simulation control
Other
1 stars 2 forks source link

Verilog fix #86

Closed mkosunen closed 6 months ago

mkosunen commented 6 months ago

This is quite crucial fix and should still be included to release 1.11

mkosunen commented 6 months ago

@Roenski test this please. It should fix all the issues related to sign handling of complex and scomplex bot in verilog and VHDL testbenches. I tested it with register_template with the same branch name.

Roenski commented 6 months ago

It fixes the signed output signals so looks good to me