TheSystemDevelopmentKit / rtl

Package for rtl (i.e. Verilog and VHDL ) simulation control
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Timescale propagation #87

Closed Roenski closed 5 months ago

Roenski commented 5 months ago

Clock period did not take into account the ability to set rtl_timescale. This is fixed.

Adds two new properties, rtl_timescale_num and rtl_timeprecision_num, which return the timescale and -precision as a floating point number.

The timescale should be added in a format <num><unit>, for example 1ns. The number can be an arbitrary integer, i.e. 10, 100, or even 33 is supported as well. Unit can be from the set ms,us,ns,ps,fs.

Clock period c_Ts is now calculated correctly in the testbench