Build hotfix

[mkosunen]

Is this still WIP? @Kovalevy @Roenski ?

What is the goal? I can figure it out, but could you clarify the logic with some comment in the source?

[Roenski]

The points of the hotfix were the following:

• For mixed-language designs, the compile order was fixed. I believe for a Verilog top design, the VHDL was compiled always before all Verilog modules. In our project, there was a situation where a VHDL module depended on a Verilog module, so when you compile VHDL first, it would cause an error as the Verilog module had not yet been compiled
• To speed up post-route netlist simulations, one should use the -vopt flag. However, rtl always adds a -novopt flag for interactive simulations, which would override any -vopt flags provided with vlogsimargs