Verilator support

[mkosunen]

The starting point of the development is verilator trials by @Roenski at about v1.8 merged to refactored structure at v1.12_RC. This most likely does not get ready by v1.12 release.

As a lot has been restructured already, the remaining thisgs to be done for Verilator are

• [x] Check verilator connectors structure NOT NEEDED
• [x] Testbench structure in C understood by verilator NOT NEEDED
• [x] Compilation and simulation commands

The main structural difference is that the testbench is neither in verilog nor VHDL. EDIT: Turned out that verilator 5.026 handles verilog testbenches without problems.

[mkosunen]

@Roenski could you test this with some of your designs and approve? Use also https://github.com/TheSystemDevelopmentKit/thesdk/pull/54

I did it with inverter, and it seems to run as with icarus.