TheSystemDevelopmentKit / rtl

Package for rtl (i.e. Verilog and VHDL ) simulation control
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Questa optimization presets #95

Closed Roenski closed 4 months ago

Roenski commented 4 months ago

This PR adds a property sim_optimization and sim_opt_dict to rtl class. They provides predefined preset options for running an optimized design. Using optimization speeds up the simulation a lot.

The presets are:

These optimizations work only for questa for the moment