Support instructions with optional operands

[ThinkOpenly]

Instructions like vle16.v have an optional "mask" operand. So, both of the following are valid:

  vle16.v vd,(rs1),vm
  vle16.v vd,(rs1)

This issue is to get this properly parsed, and to come up with a reasonable representation in JSON.

[Sanket-0510]

As far as I've understood this, you mean to say that vle16.v vd, (rs1),vm has an mask operand denoted by vm whereas vle16.v vd, (rs1) does not have any mask operand like vm but still both are valid

you want to make the presence and absence of mask operand optional. Am I correct?

[Bakugo90]

Hello @Sanket-0510 , @ThinkOpenly

As far as I've understood this, you mean to say that vle16.v vd, (rs1),vm has an mask operand denoted by vm whereas vle16.v vd, (rs1) does not have any mask operand like vm but still both are valid you want to make the presence and absence of mask operand optional. Am I correct?

I feel the same way. But additionaly, we need to analyse the instruction to propose a reasonable JSON representation to make it more readable.

Just in case, I'm right. Here's what I propose as a json:

For the "vle16.v vd,(rs1),vm" instruction:

{
  "operation": "vle16.v",
  "destination_register": "vd",
  "source_register": "rs1",
  "mask_operand": "vm",
  "is_mask_added": true
}

For the "vle16.v vd,(rs1)" instruction:

{
  "operation": "vle16.v",
  "destination_register": "vd",
  "source_register": "rs1",
  "is_mask_added": false
}

@Sanket-0510 . In case your are interested. This ressources help me understand a little bit; https://en.wikipedia.org/wiki/Vector_processor

[Sanket-0510]

Greetings @Bakugo90 Even I was thinking in the same way. We can state whether the mask is present for the given vector instruction or not. Some additional checks can also be added with respect to future needs.

I would like to suggest it this way-

{
  "instruction": "vle16.v",
  "destination": "vd",
  "source": "(rs1)",
  "mask_operand": "vm",
  "mask_present": true,
  "additional_check":  "required_check_ condition",
"additional_check_present":  "true"
}

{
  "instruction": "vle16.v",
  "destination": "vd",
  "source": "(rs1)",
  "mask_present": false,
 "additional_check":  "required_check_ condition",
"additional_check_present":  "false"
}

[ThinkOpenly]

I like the enthusiasm! Note, though, that there is already a JSON "schema" (a strong word, since this isn't really formalized) established. If you use the modified Sail in my fork of the upstream repo at https://github.com/ThinkOpenly/sail/, "json" branch, there is a new Sail backend which can be invoked as "sail -json", and is easily invoked using the "json" target in the Makefile in this project.

An example of the JSON emitted can be found in another downstream project of this one, https://github.com/ThinkOpenly/RISC-V_ISA/blob/main/src/ISA.json.

Note that the JSON emitted by "make json" here goes to the terminal (standard output) along with a large number of debug print statements, so I currently have to hand-edit it before adding it to the "RISC-V_ISA" project. (The flow is a work-in-progress.)

[ThinkOpenly]

I think this is now complete with https://github.com/ThinkOpenly/sail/commit/94e3038ebf0fb019ddde5d3b773ac5aec32cc28f. Closing.