Closed Astatine404 closed 1 year ago
Hello. Thanks for your interest in our work. The liberty library is the open-source skywater130. And the verilog netlist are synthesized and implemented using the open-source OpenROAD flow. Currently we have only uploaded the processed DGL graphs and tensors, but we will consider adding the raw netlists to this repo later.
It'll be great to have the raw netlists available too, thanks!
You can now download our raw design data from one of the following links: (7-zipped ~500MB)
https://disk.pku.edu.cn:443/link/90D8E40611678D1A24C214A1EFBA9630
https://drive.google.com/file/d/1QimU8q2cIADLBVL6GGFRm6tSBKbj3ZbB/view?usp=sharing
The archive contains:
The skywater130 PDK (in ./techlib), including liberty and lef files. The gate-level Verilog, DEF, SDC, SPEF, and SDF files for all the above 21 circuits, implemented using OpenROAD. Have fun hacking!
Hi,
Thanks for this very interesting work. I may have missed this but I did not find from where the original .lib, .v were obtained for creating the benchmark dataset.
Thanks!