This may be because I'm not using it as I'm supposed to, but it was unexpected behaviour, at least to me. This may be an edge case is "won't fix" but may warrant either stricter indications in the tutorial or warnings in the UI, and it may impact other things, so am documenting here.
Creating a voltage divider using a single fill of polyres sometimes works, sometimes doesn't. It seems like the graph is being scanned top to bottom and the rule appears to be:
if you have vertical overflow (polyres beyond the via), you wind up with useless entries like R0 in in 676.922974;
if you have horizontal overflow, it fails hard with a single resistor on VSS
This may be because I'm not using it as I'm supposed to, but it was unexpected behaviour, at least to me. This may be an edge case is "won't fix" but may warrant either stricter indications in the tutorial or warnings in the UI, and it may impact other things, so am documenting here.
Creating a voltage divider using a single fill of polyres sometimes works, sometimes doesn't. It seems like the graph is being scanned top to bottom and the rule appears to be: