bug in inverter

[mattvenn]

I haven't yet traced this - but do this to reproduce:

1/ load inverter design and observe inverting output simulation

2/ delete lower connecting metal and observe output is now always high as expected

3/ delete the n diffusion and observe output is now always low - unexpected, should remain high

here's the diff between step 2 and 3 downloaded spice

seems the pmos out now gets connected to vss

[mattvenn]

figured it out with the cross section

once the ndiff is removed, the via connects down to the substrate