Greetings, Tom. Would you consider modifying the hardware by replacing the serial-to-parallel 74HC164 ICs with a pair of cascaded 8-bit parallel 74HC574 ICs? The change would free up a few pins on the Nano and setting the address lines should be much faster. One 'downside' is that breadboard or PCB routing would be a little bit more involved.
Setting the address lines is accomplished by writing two bytes to the '574s. Note that the /OE pin is maintained high and the /CE pin should be high when setting the address latches. Set the data lines with the high address byte, strobe the /OE pin low then high, set data lines with low address byte, strobe the /OE pin low then high. After that, you can take the /OE pin low when required in order to read a byte from the ROM, however if you take it from low to high you'll corrupt the address latches.
Greetings, Tom. Would you consider modifying the hardware by replacing the serial-to-parallel 74HC164 ICs with a pair of cascaded 8-bit parallel 74HC574 ICs? The change would free up a few pins on the Nano and setting the address lines should be much faster. One 'downside' is that breadboard or PCB routing would be a little bit more involved.
Setting the address lines is accomplished by writing two bytes to the '574s. Note that the /OE pin is maintained high and the /CE pin should be high when setting the address latches. Set the data lines with the high address byte, strobe the /OE pin low then high, set data lines with low address byte, strobe the /OE pin low then high. After that, you can take the /OE pin low when required in order to read a byte from the ROM, however if you take it from low to high you'll corrupt the address latches.
Cheerful regards, Mike, K8LH (Michigan, USA)
