Closed frodare closed 7 years ago
Thoughts:
I like the rest of them.
Great points, I updated the list of candidates.
It looks like with CLR, "CLR whatever" is the same as "MOV whatever, 0", which doesn't really seem to be worth it. What I meant to add was a CLRB to do just the opposite of SETB.
The TNT
command! How horrible would that be, bwhahahah.
I don't really see the point to SEZ, CLZ, SEC, CLC, and it's easy enough to cause a fault by doing "DIV 0", so we really don't need HLT. Are they really worth having?
They were easy to add didn't take much code, so don't see a reason not to have them. I figured HLT might useful so that the processor could be clearly stopped without throwing an error. Right now the other four instructions are the only way to directly update the flags, not that I can think of a reason for doing so.
How does HLT not throw an error? It looks like it just sets "fault" to true, which is the exact same thing that happens if you do "DIV 0". (And I've never heard of an assembly language that lets you directly set those flags.)
In the end it more about clarity if you were sharing programs with other players. Right now the NEXT box on the GUI shows the first line that failed to parse in red, in the future I would like it to show the line it failed during run time too, for instance DIV 0
.
Candidates:
(memory instructions will be included in another issue)
[x] DJNZ - decrements the byte indicated by the first operand and, if the resulting value is not zero, branches to the address specified in the second operand.
[x] JC - instruction branches to the specified address if the carry flag is set. Otherwise, execution continues with the next instruction. No flags are affected by this instruction.
[x] JNC - instruction transfers program control to the specified address if the carry flag is 0. Otherwise, execution continues with the next instruction. No flags are affected by this instruction.
[x] ROR - a shift right instruction except bits that slide off the end of the register are fed back into the spaces.
[x] ROL - a shift left instruction except bits that slide off the end of the register are fed back into the spaces.
[x] SAR - arithmetic right shift, same as SHR except bits are filled in to preserve the sign of the number (int two's complement)
[x] SAL - arithmetic right shift, same as SHL
[x] HLT - Stops the processor
[x] CLZ - Clear Zero Flag
[x] CLC - Clear Carry Flag
[x] SEZ - Clear Zero Flag
[x] SEC - Clear Carry Flag
Meh?
JB - instruction branches to the address specified in the second operand if the value of the bit specified in the first operand is 1. The bit that is tested is not modified. No flags are affected by this instruction. How is a register and bit encoded in a single argument?
JNB - instruction branches to the specified address if the specified bit operand has a value of 0. Otherwise, execution continues with the next instruction. No flags are affected by this instruction. How is a register and bit encoded in a single argument?
SETB - instruction sets the bit operand to a value of 1. This instruction can operate on the carry flag or any other directly addressable bit. No flags are affected by this instruction. How is a register and bit encoded in a single argument, or is this only for flags?
CLRB - instruction sets the bit operand to a value of 0. This instruction can operate on the carry flag or any other directly addressable bit. No flags are affected by this instruction. How is a register and bit encoded in a single argument, or is this only for flags?
XCH - instruction loads the accumulator with the byte value of the specified operand while simultaneously storing the previous contents of the accumulator in the specified operand.
Unlikely
SWAP - instruction exchanges the low-order and high-order nibbles within the accumulator. No flags are affected by this instruction.
XRL - instruction performs a logical exclusive OR operation between the specified operands. The result is stored in the destination operand.(too close to XOR)