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Toyon / Chilipepper

Laboratory exercises and references designs for teaching wireless algorithm implementation in FPGAs.
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Lab2 where does the cfg file comes from ? #11

Closed DaniMA closed 11 years ago

DaniMA commented 11 years ago

Hi,

A new question I have here page10 of lab2 section 16. mention about having a cfg file that should go in the sysgen directory like lab0 and lab1. Here I don't get it lab0 and 1 HDL coder generated the cfg file and the vhdl files that where use afterward, but here I don't know where the cfg's files are supposed to come from ? Any hint ?

Other thing I get a adc_driver warning from the external connected blocks meaning the gatewayin is this expected ? ( ISE14.4 ML2013a).

Thanks enjoy the coming week-end. Daniel

dlmtoyon commented 11 years ago

Hi Daniel,

This is an error in the lab, and I've just corrected it. In general the cfg files you need are automatically created by HDL coder and by default are placed in the "/Codegen//hdlsrc" directory. These are only created however when you use HDL coder to create a custom block for your Simulink model. Since lab 2 doesn't require creating any block using MATLAB, you don’t need to do this extra step.

The warning you get about the adc_driver is normal and is caused by having Simulink library blocksets in your design. These blocks will not be exported into the Xilinx PCore, so you can ignore the warning.

Sorry for the confusion, -Damein