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Tractables / ProbabilisticCircuits.jl

Probabilistic Circuits from the Juice library
https://tractables.github.io/ProbabilisticCircuits.jl/dev
Apache License 2.0
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KeyError on SDD to PSDD compilation #80

Closed RenatoGeh closed 2 years ago

RenatoGeh commented 3 years ago

Hi,

Caught this error when trying to compile a PSDD from an SDD. Here's a minimal working example:

using LogicCircuits, ProbabilisticCircuits, Random
Random.seed!(1)
sdd = compile(SddMgr(Vtree(4, :random)), load_cnf("test.cnf"))
psdd = compile(StructProbCircuit, sdd)

Where test.cnf is as follows.

c Encodes the following: ϕ = (1 ∨ ¬2) ∧ (3 ∨ ¬4) ∧ (1 ∨ ¬4)
p cnf 4 3
1 -2 0
3 -4 0
1 -4 0

Here's the traceback:

ERROR: KeyError: key 4 not found
Stacktrace:
  [1] getindex
    @ ./dict.jl:482 [inlined]
  [2] (::LogicCircuits.var"#176#178"{Dict{Int32, LogicCircuits.LogicCircuit}})(x::Int64)
    @ LogicCircuits ~/.julia/packages/LogicCircuits/DMh1t/src/transformations.jl:82
  [3] iterate
    @ ./generator.jl:47 [inlined]
  [4] collect_to!(dest::Vector{LogicCircuits.SddMgrLeafNode}, itr::Base.Generator{Vector{Int64}, LogicCircuits.var"#176#178"{Dict{Int32, LogicCircuits.LogicCircuit}}}, offs::Int64, st::Int64)
    @ Base ./array.jl:724
  [5] collect_to_with_first!(dest::Vector{LogicCircuits.SddMgrLeafNode}, v1::LogicCircuits.SddMgrLeafNode, itr::Base.Generator{Vector{Int64}, LogicCircuits.var"#176#178"{Dict{Int32, LogicCircuits.LogicCircuit}}}, st::Int64)
    @ Base ./array.jl:702
  [6] _collect(c::Vector{Int64}, itr::Base.Generator{Vector{Int64}, LogicCircuits.var"#176#178"{Dict{Int32, LogicCircuits.LogicCircuit}}}, #unused#::Base.EltypeUnknown, isz::Base.HasShape{1})
    @ Base ./array.jl:696
  [7] collect_similar
    @ ./array.jl:606 [inlined]
  [8] map
    @ ./abstractarray.jl:2294 [inlined]
  [9] smooth_node(node::LogicCircuits.PlainStruct⋀Node, parent_scope::BitSet, scope::BitSet, lit_nodes::Dict{Int32, LogicCircuits.LogicCircuit})
    @ LogicCircuits ~/.julia/packages/LogicCircuits/DMh1t/src/transformations.jl:82
 [10] (::LogicCircuits.var"#159#165"{LogicCircuits.Utils.var"#callback#11"{Tuple{LogicCircuits.Utils.Node, BitSet}, LogicCircuits.var"#f_leaf#19"{Tuple{LogicCircuits.Utils.Node, BitSet}, LogicCircuits.var"#f_con#160", LogicCircuits.var"#f_lit#161"}, LogicCircuits.var"#f_inner#20"{Tuple{LogicCircuits.Utils.Node, BitSet}, LogicCircuits.var"#f_a#162"{Dict{Int32, LogicCircuits.LogicCircuit}}, LogicCircuits.var"#f_o#163"{Dict{Int32, LogicCircuits.LogicCircuit}}}, Dict{LogicCircuits.Utils.Dag, Tuple{LogicCircuits.Utils.Node, BitSet}}}, BitSet, Dict{Int32, LogicCircuits.LogicCircuit}})(child::LogicCircuits.PlainStruct⋀Node)
    @ LogicCircuits ~/.julia/packages/LogicCircuits/DMh1t/src/transformations.jl:36
 [11] map!(f::LogicCircuits.var"#159#165"{LogicCircuits.Utils.var"#callback#11"{Tuple{LogicCircuits.Utils.Node, BitSet}, LogicCircuits.var"#f_leaf#19"{Tuple{LogicCircuits.Utils.Node, BitSet}, LogicCircuits.var"#f_con#160", LogicCircuits.var"#f_lit#161"}, LogicCircuits.var"#f_inner#20"{Tuple{LogicCircuits.Utils.Node, BitSet}, LogicCircuits.var"#f_a#162"{Dict{Int32, LogicCircuits.LogicCircuit}}, LogicCircuits.var"#f_o#163"{Dict{Int32, LogicCircuits.LogicCircuit}}}, Dict{LogicCircuits.Utils.Dag, Tuple{LogicCircuits.Utils.Node, BitSet}}}, BitSet, Dict{Int32, LogicCircuits.LogicCircuit}}, dest::Vector{LogicCircuits.Utils.Node}, A::Vector{LogicCircuits.PlainStructLogicCircuit})
    @ Base ./abstractarray.jl:2287
 [12] (::LogicCircuits.var"#f_o#163"{Dict{Int32, LogicCircuits.LogicCircuit}})(n::LogicCircuits.PlainStruct⋁Node, call::LogicCircuits.Utils.var"#callback#11"{Tuple{LogicCircuits.Utils.Node, BitSet}, LogicCircuits.var"#f_leaf#19"{Tuple{LogicCircuits.Utils.Node, BitSet}, LogicCircuits.var"#f_con#160", LogicCircuits.var"#f_lit#161"}, LogicCircuits.var"#f_inner#20"{Tuple{LogicCircuits.Utils.Node, BitSet}, LogicCircuits.var"#f_a#162"{Dict{Int32, LogicCircuits.LogicCircuit}}, LogicCircuits.var"#f_o#163"{Dict{Int32, LogicCircuits.LogicCircuit}}}, Dict{LogicCircuits.Utils.Dag, Tuple{LogicCircuits.Utils.Node, BitSet}}})
    @ LogicCircuits ~/.julia/packages/LogicCircuits/DMh1t/src/transformations.jl:34
 [13] f_inner
    @ ~/.julia/packages/LogicCircuits/DMh1t/src/queries/queries.jl:47 [inlined]
 [14] #9
    @ ~/.julia/packages/LogicCircuits/DMh1t/src/Utils/graphs.jl:140 [inlined]
 [15] get!
    @ ./dict.jl:465 [inlined]
 [16] foldup
    @ ~/.julia/packages/LogicCircuits/DMh1t/src/Utils/graphs.jl:137 [inlined]
 [17] (::LogicCircuits.Utils.var"#callback#11"{Tuple{LogicCircuits.Utils.Node, BitSet}, LogicCircuits.var"#f_leaf#19"{Tuple{LogicCircuits.Utils.Node, BitSet}, LogicCircuits.var"#f_con#160", LogicCircuits.var"#f_lit#161"}, LogicCircuits.var"#f_inner#20"{Tuple{LogicCircuits.Utils.Node, BitSet}, LogicCircuits.var"#f_a#162"{Dict{Int32, LogicCircuits.LogicCircuit}}, LogicCircuits.var"#f_o#163"{Dict{Int32, LogicCircuits.LogicCircuit}}}, Dict{LogicCircuits.Utils.Dag, Tuple{LogicCircuits.Utils.Node, BitSet}}})(c::LogicCircuits.PlainStruct⋁Node)
    @ LogicCircuits.Utils ~/.julia/packages/LogicCircuits/DMh1t/src/Utils/graphs.jl:139
 [18] (::LogicCircuits.var"#f_a#162"{Dict{Int32, LogicCircuits.LogicCircuit}})(n::LogicCircuits.PlainStruct⋀Node, call::LogicCircuits.Utils.var"#callback#11"{Tuple{LogicCircuits.Utils.Node, BitSet}, LogicCircuits.var"#f_leaf#19"{Tuple{LogicCircuits.Utils.Node, BitSet}, LogicCircuits.var"#f_con#160", LogicCircuits.var"#f_lit#161"}, LogicCircuits.var"#f_inner#20"{Tuple{LogicCircuits.Utils.Node, BitSet}, LogicCircuits.var"#f_a#162"{Dict{Int32, LogicCircuits.LogicCircuit}}, LogicCircuits.var"#f_o#163"{Dict{Int32, LogicCircuits.LogicCircuit}}}, Dict{LogicCircuits.Utils.Dag, Tuple{LogicCircuits.Utils.Node, BitSet}}})
    @ LogicCircuits ~/.julia/packages/LogicCircuits/DMh1t/src/transformations.jl:22
 [19] f_inner
    @ ~/.julia/packages/LogicCircuits/DMh1t/src/queries/queries.jl:47 [inlined]
 [20] #9
    @ ~/.julia/packages/LogicCircuits/DMh1t/src/Utils/graphs.jl:140 [inlined]
 [21] get!
    @ ./dict.jl:465 [inlined]
 [22] foldup
    @ ~/.julia/packages/LogicCircuits/DMh1t/src/Utils/graphs.jl:137 [inlined]
 [23] callback
    @ ~/.julia/packages/LogicCircuits/DMh1t/src/Utils/graphs.jl:139 [inlined]
 [24] (::LogicCircuits.var"#158#164"{LogicCircuits.Utils.var"#callback#11"{Tuple{LogicCircuits.Utils.Node, BitSet}, LogicCircuits.var"#f_leaf#19"{Tuple{LogicCircuits.Utils.Node, BitSet}, LogicCircuits.var"#f_con#160", LogicCircuits.var"#f_lit#161"}, LogicCircuits.var"#f_inner#20"{Tuple{LogicCircuits.Utils.Node, BitSet}, LogicCircuits.var"#f_a#162"{Dict{Int32, LogicCircuits.LogicCircuit}}, LogicCircuits.var"#f_o#163"{Dict{Int32, LogicCircuits.LogicCircuit}}}, Dict{LogicCircuits.Utils.Dag, Tuple{LogicCircuits.Utils.Node, BitSet}}}})(c::LogicCircuits.PlainStruct⋀Node)
    @ LogicCircuits ~/.julia/packages/LogicCircuits/DMh1t/src/transformations.jl:32
 [25] _mapreduce(f::LogicCircuits.var"#158#164"{LogicCircuits.Utils.var"#callback#11"{Tuple{LogicCircuits.Utils.Node, BitSet}, LogicCircuits.var"#f_leaf#19"{Tuple{LogicCircuits.Utils.Node, BitSet}, LogicCircuits.var"#f_con#160", LogicCircuits.var"#f_lit#161"}, LogicCircuits.var"#f_inner#20"{Tuple{LogicCircuits.Utils.Node, BitSet}, LogicCircuits.var"#f_a#162"{Dict{Int32, LogicCircuits.LogicCircuit}}, LogicCircuits.var"#f_o#163"{Dict{Int32, LogicCircuits.LogicCircuit}}}, Dict{LogicCircuits.Utils.Dag, Tuple{LogicCircuits.Utils.Node, BitSet}}}}, op::typeof(union), #unused#::IndexLinear, A::Vector{LogicCircuits.PlainStructLogicCircuit})
    @ Base ./reduce.jl:408
 [26] _mapreduce_dim
    @ ./reducedim.jl:318 [inlined]
 [27] #mapreduce#672
    @ ./reducedim.jl:310 [inlined]
 [28] mapreduce
    @ ./reducedim.jl:310 [inlined]
 [29] (::LogicCircuits.var"#f_o#163"{Dict{Int32, LogicCircuits.LogicCircuit}})(n::LogicCircuits.PlainStruct⋁Node, call::LogicCircuits.Utils.var"#callback#11"{Tuple{LogicCircuits.Utils.Node, BitSet}, LogicCircuits.var"#f_leaf#19"{Tuple{LogicCircuits.Utils.Node, BitSet}, LogicCircuits.var"#f_con#160", LogicCircuits.var"#f_lit#161"}, LogicCircuits.var"#f_inner#20"{Tuple{LogicCircuits.Utils.Node, BitSet}, LogicCircuits.var"#f_a#162"{Dict{Int32, LogicCircuits.LogicCircuit}}, LogicCircuits.var"#f_o#163"{Dict{Int32, LogicCircuits.LogicCircuit}}}, Dict{LogicCircuits.Utils.Dag, Tuple{LogicCircuits.Utils.Node, BitSet}}})
    @ LogicCircuits ~/.julia/packages/LogicCircuits/DMh1t/src/transformations.jl:32
 [30] f_inner
    @ ~/.julia/packages/LogicCircuits/DMh1t/src/queries/queries.jl:47 [inlined]
 [31] #9
    @ ~/.julia/packages/LogicCircuits/DMh1t/src/Utils/graphs.jl:140 [inlined]
 [32] get!
    @ ./dict.jl:465 [inlined]
 [33] foldup
    @ ~/.julia/packages/LogicCircuits/DMh1t/src/Utils/graphs.jl:137 [inlined]
 [34] foldup
    @ ~/.julia/packages/LogicCircuits/DMh1t/src/Utils/graphs.jl:133 [inlined]
 [35] foldup
    @ ~/.julia/packages/LogicCircuits/DMh1t/src/queries/queries.jl:48 [inlined]
 [36] foldup
    @ ~/.julia/packages/LogicCircuits/DMh1t/src/queries/queries.jl:46 [inlined]
 [37] smooth(root::LogicCircuits.PlainStruct⋁Node)
    @ LogicCircuits ~/.julia/packages/LogicCircuits/DMh1t/src/transformations.jl:40
 [38] compile(#unused#::Type{StructProbCircuit}, sdd::LogicCircuits.Sdd⋁Node)
    @ ProbabilisticCircuits ~/.julia/packages/ProbabilisticCircuits/ppUhD/src/structured_prob_nodes.jl:136
 [39] top-level scope
    @ REPL[8]:1

Thanks

khosravipasha commented 3 years ago

The issue seems to be coming from smoothing line sstructplc = smooth(structplc). We have few other tests that work with cnfs, so either something wrong with this CNF or an edge case of smooth function. 

function compile(::Type{<:StructProbCircuit}, sdd::Sdd)::StructProbCircuit
    lc = LogicCircuit(sdd)
    plc = propagate_constants(lc, remove_unary=true)
    structplc = compile(StructLogicCircuit, vtree(sdd), plc)
    sstructplc = smooth(structplc)
    compile(StructProbCircuit, sstructplc)
end
khosravipasha commented 2 years ago

Fixed by above PR on LogicCircuits.