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Trinity-11 / FoenixIDE

Development and Debugging Suite for the C256 Foenix Family of Computers
GNU General Public License v3.0
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F256K mode: IDE horizontal scrolling does not match hardware for 8-pixel tiles #58

Closed scttgs0 closed 4 weeks ago

scttgs0 commented 2 months ago

On the hardware, all bits of the XSCROLL register (lo-nibble) are used as the scroll offset value. The IDE seems to be masking bit-0, thus, only scrolling by even values are possible.

dtremblay commented 1 month ago

From the F256K reference manual, page 40 "Tile Maps": SSX horizontal scroll in pixels. How these bits are used varies with the size. If tiles are 16 pixels wide, then flags SSX[3..0] are used. If tiles are only 8 pixels wide, then only SSX[3..1] are used. I haven't tested against the machine yet.

scttgs0 commented 1 month ago

I believe the manual is lacking some of the detail. At least it doesn't match the hardware implementation. It makes sense that only 3 bits are required to scroll 8 pixels, but the IDE is not performing a right-shift to move the bits into the [0:7] range. Instead, the IDE seems to mask bit-0 to '0' resulting in a set {0,2,4,6,8,10,12,14}... binary set {0000,0010,0100,0110,1000,1010,1100,1110}... As expected, there are 8 possible scroll values in the set, but they are always even values. e.g. It is impossible to scroll 3 pixels within the IDE.

dtremblay commented 4 weeks ago

The IDE was implementing the document, which states that bit SSX0 was not used.

What the hardware does instead is use all bits, creating a sort of overlap. This is now fixed for small tiles. I've now been made aware that there is a similar problem with large tiles.