Open Try opened 2 years ago
auto cmd = device.commandBuffer();
{
auto enc = cmd.startEncoding(device);
// ? -> write
enc.dispatch(&buf); // WAR barrier
// write -> read
enc.dispatch(const &buf); // RAW barrier
// read-> read
enc.dispatch(const &buf); // no barrier
}
auto cmd = device.commandBuffer();
{
auto enc = cmd.startEncoding(device);
// ? -> read
enc.dispatch(const &buf); // no barrier
}
auto cmd = device.commandBuffer();
{
auto enc = cmd.startEncoding(device);
// ? -> write
enc.dispatch(&buf); // WAR barrier
// write -> read, since we don't know what followup submission is going to be
}
auto cmd = device.commandBuffer();
{
auto enc = cmd.startEncoding(device);
// ? -> write
enc.dispatch(&buf);
// usage of buf in rendering?
enc.setFramebuffer(...);
enc.draw(&buf);
}
Transferring here is very much engine magic, so barriers can be explicit.
Magic function:
device.vbo
device.ibo
device.ssbo
device.loadTexture
device.readPixels
device.readBytes
`Buffer::update`
Command buffer functions:
copy(const Attachment& src, uint32_t mip, StorageBuffer& dest, size_t offset);
void generateMipmaps(Attachment& tex);
PS: At this point presumption is that, before command buffer execution, buf had eider no access or read-only access, from previous submissions.
Corner case with compute pre-pass:
auto cmd = device.commandBuffer();
{
auto enc = cmd.startEncoding(device);
// ALL -> COMP
enc.dispatch(&buf);
// COMP -> ALL
enc.setFramebuffer(...);
enc.draw(&buf);
}
Issuing all barrier is fine fox DX12 (it's just UAV barrier), but not for Vulkan. Specially not in TBR hardware. As side idea:
New idea of dependency tracking/barrier emit.
For buffers and storage images layout transition is not a needed, so coarse-grained tracking is possible. For each 'important' shader-stage engine now tracks bitmask of readed resources and written resources. This allowed to test for barrier need with a few of bit operations, with Read-Write granularity.
Currently(5cf3ca3 commit) engine distinct compute vs graphics stages, producing nice comp
-comp
barriers for dispatch
and comp
-graphics
at start of renderpass
This ticket is to track the ideas/solutions to pipeline barriers generation. Mostly it's about Vulkan perspective, yet DirectX12 is also to take in consideration.
Strategy:
All image resources assume a default read-to-read.
VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT
VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
VK_PIPELINE_STAGE_{EARLY|LATE}_FRAGMENT_TESTS_BIT
(no real layout, just ready-to-read)
VK_PIPELINE_STAGE_ALL_COMMANDS_BIT
dest stage is ALL_COMMANDS (except for Depth) for now. Compute: all storage resources are tracked individually; if current pipeline has a unordered access - new set of barriers has to be issues.
Code sample:
Points of interest
Optimize:
Problems:
Api-limitations
7.9. Host Write Ordering Guarantees
This makes it easier on resource upload/uniform buffers side, yet still command buffer must assume any commands submitted before.
7.6. Pipeline Barriers
This may cause troubles, if barriers are delayed.
7.6.1. Subpass Self-dependency
Since
VK_KHR_dynamic_rendering
is a go-to extension, barriers must not be issued in renderpass. This limitation basically blocks any split-barrier or partial-barrier approaches.