UCI-HyperXite / inverter-control

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Reorder GPIO outputs to avoid short #23

Closed samderanova closed 7 months ago

samderanova commented 7 months ago

Resolves #22. When v is 1, the low side signal is outputted first and when v is 0, the high side signal is outputted second. Note that this has a slight impact on the apparent frequency, decreasing it from 53 kHz to around 49 kHz.