Many thanks for your help before. We have a working demo with HCL-AutoSA integration now. The workflow is not fully automated right now. This issue is just to document what I have changed manually to make the flow work.
AutoSA generated HLS code run into deadlock if host (de)serialization option is turned off. So we should always keep that option on (However, serialization is not needed if the port connects to an on-chip memory. To make it work, I have to remove it manually). I tried to increase the FIFO depth (for the FIFOs inside AutoSA) a bit from 2 to 4, or even larger. Sometimes this would solve the deadlock issue, but not always.
When host serialization is turned on, some interface memory ports will be packed to bit-width not of 2's power. This will cause error in synthesis with Vitis.
The AutoSA generated code cannot be synthesized sometimes. Vitis complains that the ternary operands having ambiguous data types. To make it compliable, I need to add casting expressions manually to the macro.
// macro generated by AutoSA (trigger synthesis error)
#define min(x, y) x < y? x: y
// synthesizable version
#define min(x, y) cast(x) < cast(y)? cast(x): cast(y)
The SA's output is computed tile by tile. If we want to connect two SAs, or connect SA with another function with FIFO interface, we have to make sure the tile size matches, or we need to insert intermediate buffer manually to ensure the data access order matches. This part should be done in the HCL side, but to do this, we will need some extra information from AutoSA.
Hi,
Many thanks for your help before. We have a working demo with HCL-AutoSA integration now. The workflow is not fully automated right now. This issue is just to document what I have changed manually to make the flow work.
AutoSA generated HLS code run into deadlock if host (de)serialization option is turned off. So we should always keep that option on (However, serialization is not needed if the port connects to an on-chip memory. To make it work, I have to remove it manually). I tried to increase the FIFO depth (for the FIFOs inside AutoSA) a bit from 2 to 4, or even larger. Sometimes this would solve the deadlock issue, but not always.
When host serialization is turned on, some interface memory ports will be packed to bit-width not of 2's power. This will cause error in synthesis with Vitis.
The AutoSA generated code cannot be synthesized sometimes. Vitis complains that the ternary operands having ambiguous data types. To make it compliable, I need to add casting expressions manually to the macro.
The SA's output is computed tile by tile. If we want to connect two SAs, or connect SA with another function with FIFO interface, we have to make sure the tile size matches, or we need to insert intermediate buffer manually to ensure the data access order matches. This part should be done in the HCL side, but to do this, we will need some extra information from AutoSA.