GEMM SA Intel OpenCL code does not compile with AOC 19.2

[hecmay]

It seems that this intrinsic cannot be found with AOC 19.2

/home/u68165/temp.aoc.1024.8x8-s10/kernel.cl:948:16: error: implicit declaration of function '__burst_coalesced_load' is invalid in OpenCL
    mem_data = __burst_coalesced_load(&A[i]);
               ^
/home/u68165/temp.aoc.1024.8x8-s10/kernel.cl:948:14: error: assigning to 'A_t16' (aka 'struct A_t16_t') from incompatible type 'int'
    mem_data = __burst_coalesced_load(&A[i]);
             ^ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
/home/u68165/temp.aoc.1024.8x8-s10/kernel.cl:2543:16: warning: use of out-of-scope declaration of '__burst_coalesced_load'
    mem_data = __burst_coalesced_load(&B[i]);
               ^
/home/u68165/temp.aoc.1024.8x8-s10/kernel.cl:948:16: note: previous declaration is here
    mem_data = __burst_coalesced_load(&A[i]);

[whbldhwj]

I'm using the Intel OpenCL 20.1. It should be the newly added APIs since then. I'll add an option to eliminate using such APIs for older versions. Will notify you once I add such support.

[hecmay]

I managed to switch to 20.2, and the intrinsic not found error is solved. Here is the new error I got. It seems that the fifo_data in this L1 IO module is not declared in the scope.

void C_drain_IO_L1_out_intra_trans_0_0(C_t2 local_C[20][8])
 {
  /* Variable Declaration */
  int p0 = 0, p1 = 0; // module id
  /* Variable Declaration */

  // io_L1
  // pe
  // latency
  #pragma ivdep
  #pragma loop_coalesce
  for (uint5_t c6 = 0; c6 <= 15; c6 += 1) {
    // latency
    for (uint6_t c7 = 0; c7 <= 19; c7 += 1) {
      // simd
      // hls_pipeline
      {
        C_t1 in_data;
        C_t2 out_data;
        in_data = read_channel_intel(fifo_C_drain_PE_0_0);
        int split_idx = (c6) % 2;
        out_data = local_C[c7][c6 / 2];
        out_data.data[split_idx] = fifo_data;
        local_C[c7][c6 / 2] = out_data;
      }
    }
  }
}