FlexCNN returns all zero result

[hecmay]

Hi,

I was trying to compile the FlexCNN HLS source to an Alevo FPGA board using Vitis. I was able to get the bitstream, but when running the bitstream on HW, I found that the total execution time was too short (0.21ms), and the accelerator designs returns all zero result after the kernel is finished.

I did not change anything in the kernel code. I only changed the buffer allocation flags used in the host program a bit to bind the buffers with HBMs instead DDRs, otherwise the XRT would complain [XRT Error]: bad alloc:

  cl_mem_ext_ptr_t GlobMem_BUF_in2_Ext;
  GlobMem_BUF_in2_Ext.param = 0;
  GlobMem_BUF_in2_Ext.flags = 0 | XCL_MEM_TOPOLOGY; // XCL_MEM_DDR_BANK1;
  GlobMem_BUF_in2_Ext.obj = bias_hw.data();

All the 4 input buffers are bound to the same HBM bank, but I do not think this will affect the functionality correctness.

Do you have any suggestions on the debugging?

[atefehsz]

Hi, From the runtime, the kernel is not doing any computation at all. Have you modified the makefile? The current version binds the interfaces to DRAM banks, you should replace those with something like this: https://github.com/Xilinx/Vitis_Accel_Examples/blob/master/host/hbm_simple/krnl_vadd.ini

[hecmay]

Thanks @atefehsz!

I was using the HLS source files under the SDx_project folder. I used the example Makefile from the Vitis_Accel_Example repo. Actually I tried to bind the buffers with both storage media (i.e. DDR and HBM), but neither of those worked.

I ran into two different issues: the bitstream hangs forever after the kernel is launched. And if I kill the process and re-run it, I got the all-zero results and the kernel does not do any computation.The HW/SW emulation will cause SegFault. So I am not fully sure what is the root cause...

[atefehsz]

Could you insert print statements in the SW emulation mode to see where the SegFault happens? You can also make sure if you are reading the data that it is supposed to be read.

[hecmay]

Fixed it. The segfault is casued by a typo of the index.

I am able to launch the kernel the SW emulation now. Seems to be running, but pretty slow.

[hecmay]

I guess it is normal for the SW to be super slow. It takes around 30-40s for each layer to be processed. I can try the HW emulation and see what will happen.

[atefehsz]

I assume your problem is solved and close this issue. If you still have a problem, open a new one.

[qpchen]

Hi, Dear @Hecmay,

I also try to compile it on the Alevo FPGA board using Vitis 2020.2. But I'm stacked by the bitstream generation under the System directory. I just push the full information to issue #18.

Do you have some suggestions for that? Looking forward to your reply :-)