log2 function - for/while loop exceeding maximum number of iterations

[p-andreades]

I have the log2 function defined in a separate "functions.sv" file which is then included in the "config.sv" file only. The "functions.sv" file is not added to the synthesis project but the "config.sv" is added and it is only included in the top module file. When I try synthesizing my design, it returns an error indicating that the loop used in the log2 function has exceeded the maximum allowed number of iterations (which is in the thousands!). I get this error in both Mentor PS and Vivado..Does anyone know how to resolve this?

[DannyNicholls]

you could try using the systemverilog function $clog2(N+1) instead of your own one? And just getting rid of the functions.sv file

[DannyNicholls]

"If N can be 32 bits or larger, then the argument should be {1'b0,N}+1"

[p-andreades]

Yes, that's what I'm currently working on..thanks anyway

[DannyNicholls]

How did you get on with this? I am thinking of changing all mine to $clog2({1'b0,N}+1) wherever it is used.

[p-andreades]

It seems that Vivado allows using the $clog2 function when you declare signals and defining their bit width. However, when the function is used inside for/while loops then the synthesis fails..

[DannyNicholls]

Argh. I feel for you! I hate it when I get stumped by something that seems so simple. Have you found a solution?

I suppose one way of testing it could be to temporarily replace the offending function with the value it should be calculating whilst you synthesise and see if that works?

[DannyNicholls]

Oh hang on, so you get the same error using functions.sv as you do with $clog2()? I suppose at least that means that $clog2() can probably be used in place of functions.sv

[p-andreades]

No, I don't get the same error as I do with functions.sv. This time it doesn't complain about exceeding the max allowed number of iterations. The problem is when the function is applied dynamically on signals rather than to declare/define signals

[DannyNicholls]

Oh ok, I see what you're doing now. It would be much easier to help if you uploaded code lol. Not to worry, I'm finished now. My first exam is right at the start of the exam period.

I suppose that still means $clog2({1'b0,N}+1) is a half fix, but to dynamically assign, you need to create synthesizeable log2 code. I am sure there is an IEEE standard hdl for this somewhere, I just tried googling but can't find it.

[p-andreades]

Yes, it seems that defining a log2 function rather than using the built-in one is the way to go..I found quite a few examples on the web and in books but unfortunately they are not fully supported by the synthesis tools we are using

[DannyNicholls]

Argh! Nightmare. Hope you work it out dude.

[p-andreades]

Thanks!

[pmwatts]

How are you getting on with this, Paris? I have found a solution that works in Modelsim and MentorPS and I think it will work in vivado/ise as well. This is a one-hot to binary converter module which I found on the Altera website:

module onehot_to_bin (onehot,bin);

parameter ONEHOT_WIDTH = 16; parameter BIN_WIDTH = $clog2(ONEHOT_WIDTH-1);

input [ONEHOT_WIDTH-1:0] onehot; output [BIN_WIDTH-1:0] bin;

genvar i,j; generate for (j=0; j<BIN_WIDTH; j=j+1) begin : jl wire [ONEHOT_WIDTH-1:0] tmp_mask; for (i=0; i<ONEHOT_WIDTH; i=i+1) begin : il assign tmp_mask[i] = i[j]; end assign bin[j] = |(tmp_mask & onehot); end endgenerate

endmodule

This can be used for the dynamic cases. Then $clog2 can be used for static cases (assigning widths to arrays).

By the way, I looked at the allocator code again and there is only place where we definitely need one-hot to decimal (or dynamic log2 - they are both the same). This is when the grant matrices are converted back to binary to send back to the transmitter, as it is very inefficient to send a one-hot signal. I managed to get rid of the other dynamic log2 instance with a minor edit - I can show you tomorrow if you are around.

Phil

[p-andreades]

Thank you for your help! I will try modifying the allocator code where necessary, according to the above code example, and then try synthesizing it. Thanks once again!