pmwatts
commented
10 years ago ISE does not support SystemVerilog but the new Xilinx design tool, Vivado does. It is installed on the department systems - just type vivado in a terminal window to try it. The limitation is that Xilinx have not made it backwards compatible - it only works on the latest Virtex/Kintex-7 and Spartan-6 parts. I currently own a Virtex-7 board and have access to 2 kintex-7 shared boards.
If we want to use the Microsoft BEE3 board with 4 x Virtex-5 FPGAs, we will need to do SystemVerilog synthesis in another tool like Mentor Graphics Precision Synthesis and import into ISE or Vivado for the final layout. I have done this before - it is not too painful.
I would be opposed to rewriting in verilog. This seems like a backward step!
We should have a meeting soon and decide on FPGA requirements for the project. I have funding to buy additional 7-series boards if necessary.
Phil
On 10/24/2013 02:20 PM, Boris Dosen wrote:
To my knowledge Xilinx ISE does not support System Verilog, but only Verilog 2001.
Although this is going a bit ahead, it is something to keep in mind. I believe we will have to end up using this tool sooner or later. Is there a way around this? Or do we need to rewrite code in Verilog at some point?
— Reply to this email directly or view it on GitHub https://github.com/DannyNicholls/NetEmulation/issues/6.
Dr Philip Watts Optical Networks Group, Dept. of Electronic and Electrical Engineering, University College London Tel : +44 20 7679 2824 Email: philip.watts@ucl.ac.uk Web : www.ee.ucl.ac.uk/staff/academic/pwatts
DannyNicholls
To my knowledge Xilinx ISE does not support System Verilog, but only Verilog 2001.
Although this is going a bit ahead, it is something to keep in mind. I believe we will have to end up using this tool sooner or later. Is there a way around this? Or do we need to rewrite code in Verilog at some point?