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UCSBarchlab / PyRTL

A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Simplicity, usability, clarity, and extensibility are the overarching goals, rather than performance or optimization.
http://ucsbarchlab.github.io/PyRTL
BSD 3-Clause "New" or "Revised" License
257 stars 78 forks source link

Synchronous Reset for FPGA #162

Open jemcmahan13 opened 8 years ago

jemcmahan13 commented 8 years ago

To actually run FPGA-programmed synchronous PyRTL designs, we need some kind of reset to bring the hardware into a defined state.

Gamrix commented 8 years ago

Try this:

def add_resets(reset_wire):
    no_reset = ~ reset_wire

    def add_reset(orig_net):
        if orig_net.op != "r":
            return True

        orig_input, orig_reg = orig_net.args[0], orig_net.dests[0]
        no_reset_mask = no_reset.sign_extended(len(orig_input))
        orig_reg.reg_in = None  # to allow for a new reg assignment to occur
        orig_reg.next <<= orig_input & no_reset_mask

    net_transform(add_reset)