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UCSBarchlab / PyRTL

A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Simplicity, usability, clarity, and extensibility are the overarching goals, rather than performance or optimization.
http://ucsbarchlab.github.io/PyRTL
BSD 3-Clause "New" or "Revised" License
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Register update on Negative edge #370

Closed tahaghauri closed 3 years ago

tahaghauri commented 3 years ago

Might I request a feature for register to be able to update it's value on a negative edge clock. Something similar to verilog.

always @(negedge clk) begin
      reg <= !A;  
end
timsherwood commented 3 years ago

Hi Tahaghauri,

Once you start mixing negative edges into your design (for things other than reset) things get a bit complicated. Part of the power of pyrtl is that it restricts you somewhat from general hardware design but in doing so it frees you in other ways (to think about your hardware more like software). Typically you can rework your design to not need to do general things on both the positive and negative edge of a clock and the downstream tools will usually be happier that you did! The one place where this is really hard to change is when you need to talk to the outside world (who may be needing things on an negedge) but there we have found a little bit of hand verilog to do the adaption works pretty well. If there are specific use cases for negative edges I might not have considered I am happy to hear more about it though! Thanks for the suggestion.