UCSBarchlab / PyRTL

A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Simplicity, usability, clarity, and extensibility are the overarching goals, rather than performance or optimization.
http://ucsbarchlab.github.io/PyRTL
BSD 3-Clause "New" or "Revised" License
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Rename ISCAS bench output wires if also an input #373

Closed mdko closed 3 years ago

mdko commented 3 years ago

Some ISCAS bench files have input and output wires with the same name. This PR adds a fix to handle then in import, by renaming the output wire when needed (an alerting the user if that's the case).