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UCSBarchlab / PyRTL

A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Simplicity, usability, clarity, and extensibility are the overarching goals, rather than performance or optimization.
http://ucsbarchlab.github.io/PyRTL
BSD 3-Clause "New" or "Revised" License
254 stars 76 forks source link

Fix bug when add_reset=False; add Register tests #385

Closed mdko closed 3 years ago

mdko commented 3 years ago

Fixes issue where extra else is inserted into Verilog when add_reset=False.

Also adds tests just related to setting the reset_value in the Register initializer.

codecov-commenter commented 3 years ago

Codecov Report

Merging #385 (a0f1387) into development (c631112) will increase coverage by 0.01%. The diff coverage is 100.00%.

Impacted file tree graph

@@               Coverage Diff               @@
##           development     #385      +/-   ##
===============================================
+ Coverage        90.94%   90.96%   +0.01%     
===============================================
  Files               24       24              
  Lines             5884     5885       +1     
===============================================
+ Hits              5351     5353       +2     
+ Misses             533      532       -1
Impacted Files Coverage Δ
pyrtl/importexport.py 88.42% <100.00%> (+0.01%) :arrow_up:
pyrtl/wire.py 94.50% <0.00%> (+0.34%) :arrow_up:

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