Convenience function for importing Verilog into PyRTL via the Yosys/BLIF workflow

UCSBarchlab / PyRTL

A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Simplicity, usability, clarity, and extensibility are the overarching goals, rather than performance or optimization.

http://ucsbarchlab.github.io/PyRTL

BSD 3-Clause "New" or "Revised" License

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Convenience function for importing Verilog into PyRTL via the Yosys/BLIF workflow #393

Closed mdko closed 3 years ago

mdko commented 3 years ago

Rather than always having to remember the correct incantations to Yosys to convert a Verilog file into a PyRTL-importable BLIF file, this PR adds a function that does the Yosys script call for you, then calls input_from_blif() like normal.

mdko commented 3 years ago

We keep the same interface as input_from_blif() for consistency (i.e. taking in an open file descriptor or string containing code). This currently is skipped in CI (because the check for the presence of yosys fails); we may want to visit that so that CI installed yosys. This will have the happy effect of increasing our code coverage for this newly introduced function.