UCSBarchlab / PyRTL

A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Simplicity, usability, clarity, and extensibility are the overarching goals, rather than performance or optimization.
http://ucsbarchlab.github.io/PyRTL
BSD 3-Clause "New" or "Revised" License
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Ability to import specific module from Verilog/model from BLIF without making its io the block's IO #398

Open mdko opened 3 years ago

mdko commented 3 years ago

This will import the Verilog module without making its i/o wires the block's i/o wires. Instead, it returns an object whose attributes are input/output wires, accessible via the name of the wires defined on the Verilog module.

Given this Verilog file

module A(x, y, z);
    parameter in_size = 4;
    parameter out_size = 3;
    input [in_size-1:0] x;
    input y;
    output [out_size-1:0] z;

    assign z = x[2:0] & y;
endmodule
# ... possibly more modules

You can import it like so

with open("sample_verilog.v") as f:
    foo = pyrtl.import_from_verilog(f, toplevel="foo", parameters={'in_size': 8, 'out_size': 5}, as_block=False)

foo.x and foo.y are WireVectors, not Input, and they are named with internal names so the module can be imported multiple times without clashes. Similarly, foo.z is WireVector, not Output. All these wires can be connected to others like normal:

i, j = pyrtl.input_list('i/8 j/5')
foo.x <<= i
foo.y <<= j
pyrtl.probe(foo.z, 'out')

The key is the **as_block** parameter you pass to input_from_verilog, which will determine if block-level I/O is created, or instead a "submodule".

This PR also adds support for importing particular models from a BLIF file (since the input_from_verilog() function basically wraps the call to input_from_blif()).

codecov-commenter commented 3 years ago

Codecov Report

Merging #398 (6461ae9) into development (0e6fdae) will decrease coverage by 0.09%. The diff coverage is 78.84%.

Impacted file tree graph

@@               Coverage Diff               @@
##           development     #398      +/-   ##
===============================================
- Coverage        90.71%   90.62%   -0.10%     
===============================================
  Files               24       24              
  Lines             5988     6013      +25     
===============================================
+ Hits              5432     5449      +17     
- Misses             556      564       +8     
Impacted Files Coverage Δ
pyrtl/importexport.py 85.03% <78.84%> (-0.60%) :arrow_down:

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