Improve Verilog output when a memory doesn't have any writes

[mdko]

This continues on the improvements from #399 by doing the check for memory writes per memory, rather than across all of them, when outputting Verilog.

I.e. instead of this (the empty begin ... end):

...
    // Memory mem_0: tmp0
    always @(posedge clk)
    begin
    end
    assign tmp2 = mem_0[in1];

    // Memory mem_1: tmp1
    always @(posedge clk)
    begin
        if (const_0_1) begin
            mem_1[tmp2] <= const_1_42;
        end
    end
...

these changes now cause the following to be produced:

...
    // Memory mem_0: tmp0
    assign tmp2 = mem_0[in1];

    // Memory mem_1: tmp1
    always @(posedge clk)
    begin
        if (const_0_1) begin
            mem_1[tmp2] <= const_1_42;
        end
    end
...

[codecov-commenter]

Codecov Report

Merging #400 (0413976) into development (40f1863) will decrease coverage by 0.00%. The diff coverage is 100.00%.

@@               Coverage Diff               @@
##           development     #400      +/-   ##
===============================================
- Coverage        90.71%   90.71%   -0.01%     
===============================================
  Files               24       24              
  Lines             5990     5989       -1     
===============================================
- Hits              5434     5433       -1     
  Misses             556      556              

Impacted Files	Coverage Δ
pyrtl/importexport.py	85.65% <100.00%> (-0.03%)	:arrow_down:

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