A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Simplicity, usability, clarity, and extensibility are the overarching goals, rather than performance or optimization.
Special WireVector classes (beyond the normal Register/Const/Input/Output) like _MemIndexed, while not user-facing, end up being exposed nonetheless when used in conjunction with block methods. For example, see #405, which added a special error message to help alert the user why using the result of a memory read doesn't work as a key into the set of source/destination nets the block returns.
I suspect similar issues may occur when using a _MemIndexed as the input to a net transform, etc., so this issue is a call for further investigation and testing and possible internal rewrites to how _MemIndexed is implemented.
Special
WireVectorclasses (beyond the normalRegister/Const/Input/Output) like_MemIndexed, while not user-facing, end up being exposed nonetheless when used in conjunction with block methods. For example, see #405, which added a special error message to help alert the user why using the result of a memory read doesn't work as a key into the set of source/destination nets the block returns.I suspect similar issues may occur when using a
_MemIndexedas the input to a net transform, etc., so this issue is a call for further investigation and testing and possible internal rewrites to how_MemIndexedis implemented.