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UCSBarchlab / PyRTL

A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Simplicity, usability, clarity, and extensibility are the overarching goals, rather than performance or optimization.
http://ucsbarchlab.github.io/PyRTL
BSD 3-Clause "New" or "Revised" License
253 stars 76 forks source link

Improve BLIF importer to handle more types of dffs #413

Closed mdko closed 2 years ago

mdko commented 2 years ago

This is a fix for #411 (an issue with BLIF import where flip flops are involved).

One of the solutions proposed in #411 was to handle more of the flip-flop formats that Yosys produces (see all of them here). These changes don't handle the forms that use negedges (since PyRTL abstracts that away, we're going to assume posedge anyway), nor the _DLATCH_PN0_* latches found near the end of that file.

As future work, more tests should be added that import Verilog exercises all of these types.

codecov-commenter commented 2 years ago

Codecov Report

Merging #413 (866eccc) into development (cf5a682) will decrease coverage by 0.27%. The diff coverage is 54.83%.

Impacted file tree graph

@@               Coverage Diff               @@
##           development     #413      +/-   ##
===============================================
- Coverage        90.78%   90.51%   -0.28%     
===============================================
  Files               24       24              
  Lines             6035     6063      +28     
===============================================
+ Hits              5479     5488       +9     
- Misses             556      575      +19
Impacted Files Coverage Δ
pyrtl/importexport.py 84.03% <54.83%> (-1.62%) :arrow_down:
pyrtl/compilesim.py 91.23% <0.00%> (-0.40%) :arrow_down:
pyrtl/simulation.py 92.92% <0.00%> (-0.31%) :arrow_down:

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mdko commented 2 years ago

Closes #411.