UCSBarchlab / PyRTL

A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Simplicity, usability, clarity, and extensibility are the overarching goals, rather than performance or optimization.

http://ucsbarchlab.github.io/PyRTL

BSD 3-Clause "New" or "Revised" License

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Add unit tests for different types of possible flip-flops importable as BLIF #414

Open mdko opened 2 years ago

mdko commented 2 years ago

413 made the BLIF importer a little more robust by explicitly handling more flip-flops that Yosys might generate into the BLIF given our current Yosys script. We need to either create Verilog or BLIF files that exercise the new control paths in `extract_flop()` that are possible given those changes.

mithro commented 2 years ago

I have a spreadsheet of the various flip flops that are found in Yosys and their properties see https://docs.google.com/spreadsheets/d/16yvScRkedOkPCRBSInFuHE_cUMD8Ls-b9KFmHocpC-o/edit#gid=0

Also includes some documentation of how these map to Lattice ECP5 and Xilinx 7 Series flops too.

UCSBarchlab / PyRTL

Add unit tests for different types of possible flip-flops importable as BLIF #414

413 made the BLIF importer a little more robust by explicitly handling more flip-flops that Yosys might generate into the BLIF given our current Yosys script. We need to either create Verilog or BLIF files that exercise the new control paths in extract_flop() that are possible given those changes.