A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Simplicity, usability, clarity, and extensibility are the overarching goals, rather than performance or optimization.
When outputting your design to verilog using output_to_verilog the name of the module is always set to "toplevel". It would be great if you could pass the module name as a parameter to that function.
When outputting your design to verilog using
output_to_verilogthe name of the module is always set to "toplevel". It would be great if you could pass the module name as a parameter to that function.