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UCSBarchlab / PyRTL

A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Simplicity, usability, clarity, and extensibility are the overarching goals, rather than performance or optimization.
http://ucsbarchlab.github.io/PyRTL
BSD 3-Clause "New" or "Revised" License
253 stars 76 forks source link

`render_trace`: Display multi-wire zeroes as centered horizontal lines. #441

Closed fdxmw closed 5 months ago

fdxmw commented 5 months ago

Zero is the default value for registers, memories, and conditional assignment, so it is frequently an uninteresting value. Displaying zero as a centered horizontal line, rather than '0x0', removes a lot of visual noise from traces.

See the updated screenshots for examples.

codecov-commenter commented 5 months ago

Codecov Report

All modified and coverable lines are covered by tests :white_check_mark:

Project coverage is 91.33%. Comparing base (c9c763c) to head (3264c99).

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Additional details and impacted files ```diff @@ Coverage Diff @@ ## development #441 +/- ## =============================================== + Coverage 91.31% 91.33% +0.02% =============================================== Files 24 24 Lines 6357 6384 +27 =============================================== + Hits 5805 5831 +26 - Misses 552 553 +1 ```

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