UCSBarchlab / PyRTL

A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Simplicity, usability, clarity, and extensibility are the overarching goals, rather than performance or optimization.
http://ucsbarchlab.github.io/PyRTL
BSD 3-Clause "New" or "Revised" License
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Improve block visualization #451

Open fdxmw opened 3 months ago

fdxmw commented 3 months ago

The output of output_to_svg() is a bit hard to read. Some ideas for improvement:

  1. Use different edge colors, instead of different edge thicknesses, to distinguish single-bit wires and multi-bit wires.
  2. Use graphviz records and ports to distinguish node parameters when the order matters, like muxes, subtraction, and comparison.
  3. Try to show negation with the usual bubbles, rather than not nodes.
  4. Add bitwidth labels for multi-bit wires.
  5. Consider laying out the graph horizontally, instead of vertically. Most displays have more horizontal pixels than vertical pixels.
  6. Set the rank of inputs and outputs so inputs always appear on the left side of the graph, and outputs always appear on the right side of the graph.
  7. Try to simplify node colors and shapes. The current approach is very visually noisy.
  8. Make it easier to remove useless nodes from the graph before visualizing. Useless nodes include renaming wires that create more temporary names, slices that select all wires, and double negations (#447).